Processor with multi-level looping vector coprocessor

ABSTRACT

A processor includes a scalar processor core and a vector coprocessor core coupled to the scalar processor core. The scalar processor core includes a program memory interface through which the scalar processor retrieves instructions from a program memory. The instructions include scalar instructions executable by the scalar processor and vector instructions executable by the vector coprocessor core. The vector coprocessor core includes a plurality of execution units and a vector command buffer. The vector command buffer is configured to decode vector instructions passed by the scalar processor core, to determine whether vector instructions defining an instruction loop have been decoded, and to initiate execution of the instruction loop by one or more of the execution units based on a determination that all of the vector instructions of the instruction loop have been decoded.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority to U.S. Provisional PatentApplication No. 61/507,652, filed on Jul. 14, 2011 (Attorney Docket No.TI-70051 PS); which is hereby incorporated herein by reference in itsentirety.

BACKGROUND

Various processor designs include coprocessors that are intended toaccelerate execution of a given set of processing tasks. Some suchcoprocessors achieve good performance/area in typical processing tasks,such as scaling, filtering, transformation, sum of absolute differences,etc., executed by a digital signal processor (DSP). However, as thecomplexity of digital signal processing algorithms increases, processingtasks often require numerous passes of processing through a coprocessor,compromising power efficiency. Furthermore, access patterns required byDSP algorithms are becoming less regular, thereby negatively impactingthe overall processing efficiency of coprocessors designed toaccommodate more regular access patterns. Consequently, processor andcoprocessor architectures that provide improved processing, power,and/or area efficiency are desirable.

SUMMARY

A processor that includes a control processor core and a vectorprocessor core is disclosed herein. In one embodiment, a processorincludes a scalar processor core and a vector coprocessor core coupledto the scalar processor core. The scalar processor core includes aprogram memory interface through which the scalar processor retrievesinstructions from a program memory. The instructions include scalarinstructions executable by the scalar processor and vector instructionsexecutable by the vector coprocessor core. The vector coprocessor coreincludes a plurality of execution units and a vector command buffer. Thevector command buffer is configured to decode vector instructions passedby the scalar processor core, to determine whether vector instructionsdefining an instruction loop have been decoded, and to initiateexecution of the instruction loop by one or more of the execution unitsbased on a determination that all of the vector instructions of theinstruction loop have been decoded.

In another embodiment, a vector coprocessor includes a plurality ofexecution units and a vector command buffer. The execution units areconfigured to simultaneously apply an instruction specified operation todifferent data values. The vector command buffer is configured to decodeinstructions to be executed by the execution units, to identify aninstruction loop in the instructions, and to provide the instructions tothe execution units for execution based on a determination that all ofthe instructions of an identified instruction loop have been decoded.

In a further embodiment, a processor includes a control processor coreand a single-instruction multiple data (SIMD) coprocessor core coupledto the control processor core. The control processor core includes aprogram memory interface through which the control processor coreretrieves instructions from a program memory. The instructions compriseinstructions executable by the control processor core and SIMDinstructions executable by the SIMD coprocessor core. The SIMDcoprocessor core includes a plurality of execution units, a vectorcommand buffer, and loop control logic coupled to the vector commandbuffer. The vector command buffer is configured to group SIMDinstructions received from the control processer core into aninstruction loop, and to initiate execution of the instruction loopbased on a complete set of SIMD instructions of an instruction loopbeing received from the control processor core. The loop control logicis configured to manage execution of the instruction loop as a pluralityof nested loops without loop overhead.

BRIEF DESCRIPTION OF THE DRAWINGS

For a detailed description of exemplary embodiments of the invention,reference will now be made to the accompanying drawings in which:

FIG. 1 shows a block diagram of a processor in accordance with variousembodiments;

FIG. 2 shows a block diagram of a processor in accordance with variousembodiments;

FIG. 3 shows a block diagram of a vector coprocessor core in accordancewith various embodiments;

FIG. 4 show a block diagram of an vector command buffer of the vectorcoprocessor core in accordance with various embodiments;

FIG. 5 shows a diagram of scalar processor core and vector coprocessorcore execution interaction in accordance with various embodiments;

FIGS. 6A-6FH show load data distributions provided by a load unit of avector coprocessor core in accordance with various embodiments;

FIG. 7 shows a table of load unit data distributions in accordance withvarious embodiments; and

FIG. 8 shows a table of store unit data distributions in accordance withvarious embodiments.

NOTATION AND NOMENCLATURE

Certain terms are used throughout the following description and claimsto refer to particular system components. As one skilled in the art willappreciate, companies may refer to a component by different names. Thisdocument does not intend to distinguish between components that differin name but not function. In the following discussion and in the claims,the terms “including” and “comprising” are used in an open-endedfashion, and thus should be interpreted to mean “including, but notlimited to . . . ” Also, the term “couple” or “couples” is intended tomean either an indirect or direct electrical connection. Thus, if afirst device couples to a second device, that connection may be througha direct electrical connection, or through an indirect electricalconnection via other devices and connections. Further, the term“software” includes any executable code capable of running on aprocessor, regardless of the media used to store the software. Thus,code stored in memory (e.g., non-volatile memory), and sometimesreferred to as “embedded firmware,” is included within the definition ofsoftware. The recitation “based on” is intended to mean “based at leastin part on.” Therefore, if X is based on Y, X may be based on Y and anynumber of other factors. The terms “alternate,” “alternating” and thelike are used to designate every other one of a series.

DETAILED DESCRIPTION

The following discussion is directed to various embodiments of theinvention. Although one or more of these embodiments may be preferred,the embodiments disclosed should not be interpreted, or otherwise used,as limiting the scope of the disclosure, including the claims. Inaddition, one skilled in the art will understand that the followingdescription has broad application, and the discussion of any embodimentis meant only to be exemplary of that embodiment, and not intended tointimate that the scope of the disclosure, including the claims, islimited to that embodiment.

Embodiments of the processor disclosed herein provide improvedperformance without sacrificing area or power efficiency. FIG. 1 shows ablock diagram of a processor 100 in accordance with various embodiments.The processor 100 includes a scalar processor core 102, a vectorcoprocessor core 104, a program memory 106, a data memory 108, a workingbuffer memory 110, an A buffer memory 112, and a B buffer memory 114.The A and B buffer memories 112, 114 are partitioned into a low and highA buffer memory (112A, 112B) and a low and high B buffer memory (114A,114B) to allow simultaneous direct memory access (DMA) and access by thecores 102, 104. To support N-way processing by the vector coprocessorcore 102, each of the working buffer memory 110, A buffer memory 112,and B buffer memory 114 may comprise N simultaneously accessible banks.For example, if the vector coprocessor core 104 is an 8-waysingle-instruction multiple-data (SIMD) core, then each of the working,A, and B buffers 110, 112, 114 may comprise 8 banks each of suitableword width (e.g., 32 bits or more wide) that are simultaneouslyaccessible by the vector coprocessor core 104. Switching network 118provide signal routing between the memories 108, 110, 112, 114 and thevarious systems that share access to memory (e.g., DMA and the processorcores 102, 104).

FIG. 2 shows a block diagram of the processor 100 including variousperipherals, including DMA controller 202, memory management units 204,clock generator 206, interrupt controller 208, counter/time module 210,trace port 214, memory mapped registers 212 and various interconnectstructures that link the components of the processor 100.

The scalar processor core 102 may be a reduced instruction set processorcore, and include various components, such as execution units,registers, instruction decoders, peripherals, input/output systems andvarious other components and sub-systems. Embodiments of the scalarprocessor core 102 may include a plurality of execution units thatperform data manipulation operations. For example, an embodiment of thescalar processor core 102 may include five execution units, a firstexecution unit performs the logical, shift, rotation, extraction,reverse, clear, set, and equal operations, a second execution unitperforms data movement operations, a third execution unit performsarithmetic operations, a fourth execution unit performs multiplication,and a fifth execution unit performs division. In some embodiments, thescalar processor core 102 serves as a control processor for theprocessor 100, and executes control operations, services interrupts,etc., while the vector coprocessor core 104 serves as a signal processorfor processing signal data (e.g., image signals) provided to the vectorcoprocessor core 104 via the memories 110, 112, 114.

The program memory 106 stores instructions to be executed by the scalarcore 102 interspersed with instructions to be executed by the vectorcoprocessor core 104. The scalar processor core 102 accesses the programmemory 106 and retrieves therefrom an instruction stream comprisinginstructions to be executed by the scalar processor core 102 andinstructions to be executed by the vector coprocessor core 104. Thescalar processor core 102 identifies instructions to be executed by thevector coprocessor core 104 and provides the instructions to the vectorcoprocessor core 104 via a coprocessor interface 116. In someembodiments, the scalar processor 102 provides vector instructions,control data, and/or loop instruction program memory addresses to thevector coprocessor core 104 via the coprocessor interface 116. The loopinstruction program memory addresses may be provided concurrently with aloop instruction, and the control data may be provided concurrently witha control register load instruction. In some embodiments, the programmemory 106 may be a cache memory that fetches instructions from a memoryexternal to the processor 100 and provides the instructions to thescalar processor core 102.

FIG. 3 shows a block diagram of the vector coprocessor core 104 inaccordance with various embodiments. The vector coprocessor core 104 maybe an SIMD processor that executes instructions arranged as a loop. Morespecifically, the vector coprocessor core 104 executes vectorinstructions within a plurality of nested loops. In some embodiments,the vector coprocessor core 104 includes built-in looping control thatexecutes instructions in four or more nested loops with zero loopingoverhead. The vector coprocessor core 104 includes a commanddecoder/buffer 302, loop control logic 304, a vector register file 306,processing elements 308, a table look-up unit 310, a histogram unit 312,load units 314, store units 316, and address generators 318. The loadunits 314 and store units 316 access the working buffer memory 110, an Abuffer memory 112, and a B buffer memory 114 through a memory interface320. The address generators 318 compute the addresses applied by theload and store units 314, 316 for accessing memory. Each addressgenerator 318 is capable of multi-dimensional addressing that computesan address based on the indices of the nested loops and correspondingconstants (e.g., address=base+i₁*const₁+i₂*const₂+i₃*const₃+i₄*const₄for 4-dimensional addressing where i_(n) is a loop index for one of fournested loops).

The memory interface 320 connects the vector coprocessor core 104 via alane of interconnect corresponding to each bank of each of memories 110,112, 114. Thus, a memory 110, 112, 114 having eight parallel banks(e.g., 32-bit banks) connects to the vector coprocessor core 104 viaeight parallel memory lanes, where each memory lane connects to a portof the memory interface 320. Memory lanes that connect to adjacent portsof the memory interface 320 are termed adjacent memory lanes.

The vector coprocessor core 104 is N-way SIMD, where in the embodimentof FIG. 3, N=8. N may be different in other embodiments. Thus, thecoprocessor core 104 includes N processing lanes, where each laneincludes a processing element 308 and a set of registers of the vectorregister file 306 that provide operands to and store results generatedby the processing element 308. Each processing element 308 may include aplurality of function units that operate on (e.g., multiply, add,compare, etc.) the operands provided by the register file 306.Accordingly, the register file 306 is N-way and includes storage of aplurality of entries. For example, the register file 306 may be N×16where the register file includes sixteen registers for each of the Nways of the vector coprocessor core 104. Corresponding registers ofadjacent ways are termed adjacent registers. Thus, a register RO of SIMDway 0 is adjacent to register RO of SIMD way 1. Similarly, register ROof SIMD way 0 and register 0 of SIMD way 2 are alternate registers. Theprocessing elements 308 and the registers of the register file 306 aresized to process data values of various sizes. In some embodiments, theprocessing elements 308 and the registers of the register file 306 aresized to process 40 bit and smaller data values (e.g., 32 bit, 16 bit,8, bit). Other embodiments may be sized to process different data valuesizes.

As noted above, the vector coprocessor core 104 repeatedly executes avector instruction sequence (referred to as a vector command) within anested loop. The nested looping is controlled by the loop control logic304. While the vector coprocessor core 104 is executing vector commands,the scalar core 102 continues to decode and execute the instructionstream retrieved from program memory 106, until execution of acoprocessor synchronization instruction (by the scalar core 102) forcesthe scalar core 102 to stall for vector coprocessor core 104 vectorcommand completion. While the scalar core 102 is stalled, the scalarcore 102 may service interrupts unless interrupt processing is disabled.Thus, the scalar core 102 executes instructions and services interruptsin parallel with vector coprocessor core 104 instruction execution.Instruction execution by the scalar core 102 may be synchronized withinstruction execution by the vector coprocessor core 104 based on thescalar core 102 executing a synchronization instruction that causes thescalar core 102 to stall until the vector coprocessor core 104 asserts asynchronization signal indicating that vector processing is complete.Assertion the synchronization signal may be triggered by execution of asynchronization instruction by the vector coprocessor core 104.

The command decode/buffer 302 of the vector coprocessor core 104includes an instruction buffer that provides temporary storage forvector instructions. FIG. 4 shows a block diagram of the commanddecode/buffer 302 of the vector coprocessor core 104 in accordance withvarious embodiments. The command decode/buffer 302 includes a pre-decodefirst-in first-out (FIFO) buffer 402, a vector instruction decoder 404,and vector command storage buffers 406. Each vector command storagebuffer 406 includes capacity to store a complete vector command ofmaximum size. Vector instructions flow from the scalar processor core102 through the pre-decode FIFO 402 and are decoded by the vectorinstruction decoder 404. The decoded vector instructions correspondingto a given vector command are stored in one of the vector commandstorage buffers 406, and each stored vector command is provided forexecution in sequence. Execution of a decoded vector command isinitiated (e.g., the vector command is read out of the vector commandstorage buffer 406) only after the complete vector command is decodedand stored in a vector command storage buffer 406. Thus, the commanddecode/buffer 302 loads a vector command into each of the vector commandstorage buffers 406, and when the vector command storage buffers 406 areoccupied additional vector instructions received by the commanddecode/buffer 302 are stored in the pre-decode buffer 402 untilexecution of a vector command is complete, at which time the FIFObuffered vector command may be decoded and loaded into the emptiedvector command storage buffer 406 previously occupied by the executedvector command.

FIG. 5 shows a diagram of scalar processor core 102 and vectorcoprocessor core 104 interaction in accordance with various embodiments.In FIG. 5, vector instructions i0-i3 form a first exemplary vectorcommand, vector instructions i4-i7 form a second exemplary vectorcommand, and vector instructions i8-i11 form a third exemplary vectorcommand. At time T1, the scalar processor core 102 recognizes vectorinstructions in the instruction stream fetched from program memory 106.In response, the scalar processor core 102 asserts the vector validsignal (vec_valid) and passes the identified vector instructions to thevector coprocessor core 104. At time T2, the first vector command hasbeen transferred to the vector coprocessor core 104, and the vectorcoprocessor core 104 initiates execution of the first vector commandwhile the scalar processor core 102 continues to transfer the vectorinstructions of the second vector command to the vector coprocessor core104. At time T3, transfer of the second vector command to the vectorcoprocessor core 104 is complete, and the execution of the first vectorcommand is ongoing. Consequently, the vector coprocessor core 104negates the ready signal (vec_rdy) which causes the scalar processorcore 102 to discontinue vector instruction transfer. At time T4,execution of the first vector command is complete, and execution of thesecond vector command begins. With completion of the first vectorcommand, vector coprocessor core 104 asserts the ready signal, and thecommand decode/buffer 302 receives the vector instructions of the thirdvector command. At time T5, the vector coprocessor core 104 completesexecution of the second vector command. At time T6, transfer of thethird vector command is complete, and the vector coprocessor core 104initiates execution of the third vector command. A VWDONE instructionfollows the last instruction of the third vector command. The VWDONEinstruction causes the scalar processor core 102 to stall pendingcompletion of the third vector command by the vector coprocessor core104. When the vector coprocessor core 104 completes execution of thethird vector command, the vector coprocessor core 104 executes theVWDONE command which causes the vector coprocessor core 104 to assertthe vector done signal (vec_done). Assertion of the vector done signalallows the scalar processor core 102 to resume execution, thus providingcore synchronization.

In order to highlight certain aspects of scalar processor core 102 andvector coprocessor core 104 interaction, the example of FIG. 5 excludesthe pre-decode FIFO 402. With inclusion of the pre-decode FIFO 402, thevector coprocessor core 104 delays negation of vec_rdy until thepre-decode FIFO 402 is full.

Within the multi-level nested loop executed by the vector coprocessorcore 104, operations of vector command execution can be represented assequential load, arithmetic operation, store, and pointer update stages,where a number of operations may be executed in each stage. Thefollowing listing shows a skeleton of the nested loop model for a fourloop embodiment of the vector coprocessor core 104. There are 4 loopvariables, i1, i2, i3, and i4. Each loop variable is incremented from 0to Ipend1 . . . 4.

EVE_compute(...) {   for (i1=0; i1<=lpend1; i1++) {   for (i2=0;i2<=lpend2; i2++) {     for (i3=0; i3<=lpend3; i3++) {      for (i4=0;i4<=lpend4; i4++) {       for (k=0; k<num_inits; k++)       initialize_vreg_from_parameters(...);       for (k=0;k<num_loads; k++)        load_vreg_from_local_memory(...);       for(k=0; k<num_ops; k++)        op(...); // 2 functional units, executing 2ops per             cycle       for (k=0; k<num_stores; k++)       store_vreg_to_local_memory(...);       for (k=0; k<num_agens;k++)        update_agen(...);      }     }   } }

Each iteration of the innermost loop (i4) executes in a number of cyclesequal to the maximal number of cycles spent in execution of loads,arithmetic operations, and stores within the loop. Cycle count for thearthmetic operations is constant for each interation, but cycle countfor load and store operations can change depending on pointer update,loop level, and read/write memory contention.

Embodiments define a vector command with a loop initiation instruction,VLOOP.

-   VLOOP cmd_type, CL#: cmd_len, PL#: param_len    where:    -   cmd_type specifies the loop type: compute (executed by the        processing elements), table lookup (executed by the table lookup        unit), or histogram (executed by the histogram unit);    -   cmd_len specifies the length of the vector command; and    -   param_len specifies the length of the memory stored parameter        file associated with the vector command.

The vector instructions following VLOOP initialize the registers andaddress generators of the vector coprocessor core 104, and specify theload operations, arithmetic and data manipulation operations, and storeoperations to be performed with the nested loops. The parametersapplicable to execution of a vector command (e.g., loop counts, addresspointers to arrays, constants used in the computation, round/truncateshift count, saturation bounds, etc.) may stored in memory (e.g., 110,112, 114) by the scalar processor core 102 as a parameter file andretrieved by the vector coprocessor core 102 as part of loopinitialization.

While embodiments of the vector coprocessor core 104 may always executea fixed number of nested loops (e.g., 4 as shown in the model above),with loop terminal counts of zero or greater, some embodiments includean optional outermost loop (e.g., an optional fifth loop). The optionaloutermost loop encompasses the fixed number of nested loops associatedwith the VLOOP instruction, and may be instantiated separately from thefixed number of nested loops. As with the nested loops associated withthe VLOOP instruction, execution of the optional outermost loop requiresno looping overhead. Each iteration of the optional outermost loop mayadvance a parameter pointer associated with the nested loops. Forexample, the parameter pointer may be advanced by param_len provided inthe VLOOP instruction. The parameter pointer references the parameterfile that contains the parameters applicable to execution of the vectorcommand as explained above (loop counts, etc.). By changing theparameters of the vector command with each iteration of the outermostloop, embodiments of the vector coprocessor core 104 can apply thevector command to objects/structures/arrays of varying dimension orhaving varying inter-object spacing. For example, changing loop countsfor the nested loops allows the vector coprocessor core 104 to processesobjects of varying dimensions with a single vector command, and withoutthe overhead of a software loop.

The loop count of the optional outer loop and the parameter pointer maybe set by execution of an instruction by the vector coprocessor core104. The instruction may load a parameter into a control register of thecore 104 as:

-   VCTRL <scalar_register>, <control_register>    where:    -   scalar_register specifies a register containg a value to loaded        as an outermost loop count or parameter pointer; and    -   control_register specifies a destination register, where the        destination register may be the outermost loop end count        register or the vector command parameter pointer register.

Execution of a vector command may be complete when a total number ofiterations specified in the parameter file for each loop of the vectorcommand are complete. Because it is advantageous in some situations toterminate the vector command prior to execution of all specified loopiterations, the vector coprocessor core 104 provides early terminationof a vector command. Early termination is useful when, for example, thevector command has identified a condition in the data being processedthat makes additional processing of the data superfluous. Earlytermination of a vector command is provided for by execution, in thevector command, of a loop early exit instruction defined as:

-   VEXITNZ level, src1    where:    -   level specifies whether a vector command (i.e., loops associated        with a VLOOP instruction) or an optional outermost loop is to be        exited; and    -   src1 specifies a register containing a value that determines        whether to perform the early exit.

Execution of the VEXITNZ instruction causes the vector coprocessor core104 to examine the value contained in the register src1 (e.g.,associated with a given SIMD lane), and to schedule loop termination ifthe value is non-zero. Other embodiments may schedule loop terminationbased on other conditions of the value (e.g., zero, particular bit set,etc.). If the level parameter indicates that the vector command is to beexited, then the vector coprocessor core 104 schedules the nested loopsassociated with the vector command to terminate after completion of thecurrent iteration of the innermost of the nest loops. Thus, if the levelparameter indicates that the vector command is to be exited, anyoptional outmost loop encompassing the vector command is not exited, anda next iteration of the vector command may be executed.

If the level parameter indicates that the optional outermost loop is tobe exited, then, on identification of the terminal state of src1, thevector coprocessor core 104 schedules the optional outermost loop toterminate after completion of all remaining iterations of the nestedloops associated with the vector command encompassed by the optionaloutermost loop.

The load units 314 move data from the memories 110, 112, 114 to theregisters of the vector register file 306, and include routing circuitrythat distributes data values retrieved from the memories 110, 112, 114to the registers in various patterns that facilitate efficientprocessing. Load instructions executed by the vector coprocessor core104 specify how the data is to be distributed to the registers. FIGS.6A-6FH show load data distributions provided by the load unit 314 of thevector coprocessor core 104 in accordance with various embodiments.While the illustrative distributions of FIGS. 6A-6F are directed loadingdata values of a given size (e.g., 16 bits), embodiments of the loadunits 314 may apply similar distributions to data values of other sizes(e.g., 8 bits, 32 bits, etc.). The load units 314 may move data frommemory 110, 112, 114 to the vector registers 306 with instructionspecified distribution in a single instruction cycle.

FIG. 6A shows a load unit 314 retrieving a data value from each of eightlocations of a memory 110, 112, 114, (e.g., a value from each of eightbanks) via eight adjacent lanes and distributing the retrieved datavalues to eight adjacent registers of the vector register file 306(e.g., a register corresponding to each SIMD lane). More generally, theload unit 314 moves a value from memory via each of a plurality adjacentlanes, and distributes the data values to a plurality of adjacentregisters of the vector register file 306 in a single instruction cycle.

FIG. 6B shows a load unit 314 retrieving a data value from a singlelocation of a memory 110, 112, 114, and distributing the retrieved datavalue to each of eight adjacent registers of the vector register file306. More generally, the load unit 314 moves a value from a singlelocation of a memory 110, 112, 114, and distributes the data value to aplurality of adjacent registers of the vector register file 306 in asingle instruction cycle. Thus, the load unit 314 may distribute asingle value from memory 110, 112, 114 to each of N ways of the vectorcoprocessor core 104.

FIG. 6C shows a load unit 314 retrieving a data value from each of twolocations of a memory 110, 112, 114 via adjacent lanes, and distributingthe retrieved data values to each of four adjacent pairs of registers ofthe vector register file 306. More generally, the load unit 314 moves avalue from each of two locations of a memory 110, 112, 114 via adjacentlanes, and distributes the data value to a plurality of adjacent pairsof registers of the vector register file 306 in a single instructioncycle. That is, each value of the pair of values is written to alternateregisters of the register file 306 (e.g., one value to odd indexedregisters and the other value to even indexed registers). Thus, the loadunit 314 may distribute a pair of values from memory 110, 112, 114 toeach of N/2 way pairs of the vector coprocessor core 104.

FIG. 6D shows a load unit 314 retrieving a data value from each of eightlocations of a memory 110, 112, 114 via alternate lanes (e.g., from oddindexed locations or even indexed locations), and distributing theretrieved data values to eight adjacent registers of the vector registerfile 306. More generally, the load unit 314 moves a value from each of aplurality of locations of a memory 110, 112, 114 via alternate lanes,and distributes the data values to a plurality of adjacent registers ofthe vector register file 306 in a single instruction cycle. Thus, theload unit 314 provides down-sampling of the data stored in memory by afactor of two.

FIG. 6E shows a load unit 314 retrieving a data value from each of fourlocations of a memory 110, 112, 114 via adjacent lanes, and distributingeach of the retrieved data values to two adjacent registers of thevector register file 306. More generally, the load unit 314 moves avalue from each of a plurality locations of a memory 110, 112, 114 viaadjacent lanes, and distributes each of the data values to two adjacentregisters of the vector register file 306 in a single instruction cycle.Thus, the load unit 314 provides up-sampling of the data stored inmemory by a factor of two.

FIG. 6F shows a load unit 314 retrieving a data value from each ofsixteen locations of a memory 110, 112, 114 via adjacent lanes, anddistributing each of the retrieved data values to registers of thevector register file 306 such that data values retrieved via evennumbered lanes are distributed to adjacent registers and data valuesretrieved via odd numbered lanes are distributed to adjacent registers.More generally, the load unit 314 moves a value from each of a pluralitylocations of a memory 110, 112, 114 via adjacent lanes, and distributesthe data values in deinterleaved fashion to two sets of adjacentregisters of the vector register file 306. Thus, the load unit 314provides deinterleaving of data values across registers M and M+1 whereregister M encompasses a given register of each way of the N-way vectorcoprocessor core 104 in a single instruction cycle.

Some embodiments of the load unit 314 also provide custom distribution.With custom distribution, the load unit 314 distributes one or more datavalues retrieved from a memory 110, 112, 114 to registers of the vectorregister file 306 in accordance with a distribution pattern specified byan instruction loaded distribution control register or a distributioncontrol structure retrieved from memory. Load with custom distributioncan move data from memory to the vector register file 306 in a singleinstruction cycle. The custom distribution may be arbitrary. Customdistribution allows the number of values read from memory, the number ofregisters of the register file 306 loaded, and the distribution of datato the registers to be specified. In some embodiments of the load unit314, custom distribution allows loading of data across multiple rows ofthe vector register file 306 with instruction defined distribution. Forexample, execution of a single custom load instruction may cause a loadunit 314 to move values from memory locations 0-7 to registers V[0][0-7]and move values from memory locations 3-10 to registers V[1][0-7]. Suchdata loading may be applied to facilitate motion estimation searching ina video system.

Some embodiments of the load unit 314 further provide for loading withexpansion. In loading with expansion, the load unit 314 retrieves acompacted (collated) array from a memory 110, 112, 114 and expands thearray such the elements of the array are repositioned (e.g., toprecompacted locations) in registers of the vector register file 306.The positioning of each element of the array is determined by expansioninformation loaded into an expansion control register via instruction.For example, given array {A,B,C} retrieved from memory and expansioncontrol information {0,0,1,0,1,1,0,0}, the retrieved array may beexpanded to {0,0,A,0,B,C,0,0} and written to registers of the registerfile 306. Load with expansion moves data from memory to the vectorregister file 306 with expansion in a single instruction cycle.

FIG. 7 shows a table of data distributions that may be implemented bythe load unit 314 in accordance with various embodiments. Operation ofthe load units 314 may be invoked by execution of a vector loadinstruction by the vector coprocessor core 104. The vector loadinstruction may take the form of:

-   VLD<type>_<distribution> base[agen], vreg    where:    -   type specifies the data size (e.g., byte, half-word, word,        etc.);    -   distribution specifies the data distribution option (described        above) to be applied;    -   base specifies a register containing an address;    -   agen specifies an address generator for indexing; and    -   vreg specifies a vector register to be loaded.

The timing of vector load instruction execution may be determined by theload units 314 (i.e., by hardware) based, for example, on when the dataretrieved by the load is needed by the processing elements 308, andmemory interface availability. In contrast, the timing of thecomputations performed by the processing elements 308 may be determinedby the sequence of vector instructions provided by the scalar processorcore 102.

The store units 316 include routing circuitry that distributes datavalues retrieved from the registers of the vector register file 306 tolocations in the memories 110, 112, 114 in various patterns thatfacilitate efficient processing. Store instructions executed by thevector coprocessor core 104 specify how the data is to be distributed tomemory. At least some of the data distributions provide by the storeunit 316 reverse the data distributions provided by the load units 314.The store units 316 may provide the data distributions described hereinfor data values of various lengths (e.g., 32, 16, 8 bit values). Thestore units 316 move data from the vector registers 306 to memory 110,112, 114 with instruction specified distribution in a single instructioncycle.

A store unit 316 may move data from a plurality of adjacent registers ofthe register file 306 to locations in memory 110, 112, 114 via adjacentmemory lanes in a single instruction cycle. For example, data valuescorresponding to a given register of each of N-ways of the vectorcoprocessor core 104 may be moved to memory via adjacent memory lanes ina single instruction cycle. The store unit 316 may also move a valuefrom a single given register of the register file 306 to a givenlocation in memory 110, 112, 114 in a single instruction cycle.

The store unit 316 may provide downsampling by a factor of two bystoring data retrieved from alternate registers of the vector registerfile 306 (i.e., data from each of alternate ways of the vectorcoprocessor core 104) to locations of memory 110, 112, 114 via adjacentmemory lanes. Thus, the store unit 316 may provide an operation thatreverses the upsampling by two shown in FIG. 6E. The store unit 316provides the movement of data from registers to memory with downsampling in a single instruction cycle.

Embodiments of the store unit 316 may provide interleaving of datavalues retrieved from registers of the vector register file 306 whilemoving the data values to memory. The interleaving reverses thedistribution shown in FIG. 6F such that data values retrieved from afirst set of adjacent registers are written to memory locations via evenindexed memory lanes and data values retrieved from a second set ofadjacent registers are interleaved therewith by writing the data valuesto memory locations via odd indexed memory lanes. The store unit 316provides the movement of data from registers to memory with interleavingin a single instruction cycle.

Embodiments of the store unit 316 may provide for transposition of datavalues retrieved from registers of the vector register file 306 whilemoving the data values to memory, where, for example, the data valuesform a row or column of an array. Data values corresponding to each wayof the vector coprocessor core 104 may be written to memory at an indexcorresponding to the index of the register providing the data valuetimes the number of ways plus one. Thus, for 8-way SIMD, reg[0] iswritten to mem[0], reg[1] is written to mem[9], reg[2] is written tomem[18], etc. Where, the transposed register values are written todifferent banks of memory, the store unit 316 provides movement of Ndata values from registers to memory with transposition in a singleinstruction cycle.

Embodiments of the store unit 316 may provide collation of data valuesretrieved from registers of the vector register file 306 while movingthe data values to memory. The collating reverses the expansiondistribution provided by the load units 314. The collation compacts thedata retrieved from adjacent registers of the vector register file 306,by writing to locations of memory via adjacent memory lanes those datavalues identified in collation control information stored in a register.For example, given registers containing an array {0,0,A,0,B,C,0,0} andcollation control information {0,0,1,0,1,1,0,0}, the store unit 316stores {A,B,C} in memory. The store unit 316 provides the movement ofdata from registers to memory with collation in a single instructioncycle.

Embodiments of the store unit 316 may provide data-driven addressing(DDA) of data values retrieved from registers of the vector registerfile 306 while moving the data values to memory. The data-drivenaddressing generates a memory address for each of a plurality ofadjacent registers of the vector register file 306 using offset valuesprovided from a DDA control register. The DDA control register may be aregister of the vector register file corresponding the way of theregister containing the value to written to memory. Register data valuescorresponding to each of the N ways of the vector coprocessor core maybe stored to memory in a single instruction cycle if the DDA controlregister specified offsets provide for the data values to be written todifferent memory banks. If the DDA control register specified offsetsprovide for the data values to be written to memory banks that precludesimultaneously writing all data values, then the store unit 316 maywrite the data values in a plurality of cycles selected to minimize thenumber of memory cycles used to write the register values to memory.

Embodiments of the store unit 316 may provide for moving data valuesretrieved from a plurality of adjacent registers of the vector registerfile 306 to locations of the memory via alternate memory lanes, thusskipping every other memory location. The store units 316 may write theplurality of data values to alternate locations in memory 110, 112, 114in a single instruction cycle.

FIG. 8 shows a table of data distributions that may be implemented bythe store unit 316 in accordance with various embodiments. Operation ofthe store units 316 may be invoked by execution of a vector storeinstruction by the vector coprocessor core 104. The vector storeinstruction may take the form of:

-   [pred] VST<type>_<distribution>_<wr_loop> vreg, base[agen], RND_SAT:    rnd_sat_param    where:    -   pred specifies a register containing a condition value that        determines whether the store is performed;    -   type specifies the data size (e.g., byte, half-word, word,        etc.);    -   distribution specifies the data distribution option to be        applied;    -   wr_loop specifies the nested loop level where the store is to be        performed;    -   vreg specifies a vector register to be stored;    -   base specifies a register containing an address;    -   agen specifies an address generator for indexing; and    -   RND_SAT: rnd_sat_param specifies the rounding/saturation to be        applied to the stored data.

The store units 316 provide selectable rounding and/or saturation ofdata values as the values are moved from the vector registers 306 tomemory 110, 112, 114. Application of rounding/saturation adds noadditional cycles to the store operation. Embodiments may selectablyenable or disable rounding. With regard to saturation, embodiments mayselectably perform saturation according to following options:

-   -   NO_SAT: no saturation performed;    -   SYMM: signed symmetrical saturation [−bound, bound] (for        unsigned store, [0, bound]);    -   ASYMM: signed asymmetrical saturation [−bound−1, bound] (for        unsigned store, [0, bound]), useful for fixed bit width. For        example, when bound=1023, saturate to [−1024, 1023];    -   4PARAM: use 4 parameter registers to specify sat_high_cmp,        sat_high_set, sat_(—low) _(—cmp, sat) _(—low) _(—set;)    -   SYMM32: use 2 parameter registers to specify a 32-bit bound,        then follow SYMM above; and    -   ASYMM32: use 2 parameter registers to specify a 32-bit bound,        then follow ASYMM above.

The timing of vector store instruction execution is determined by thestore units 316 (i.e., by hardware) based, for example, on availabilityof the memories 110, 112, 114. In contrast, the timing of thecomputations performed by the processing elements 308 may be determinedby the sequence of vector instructions provided by the scalar processorcore 102.

The processing elements 308 of the vector coprocessor core 104 includelogic that accelerates SIMD processing of signal data. In SIMDprocessing, each of the N processing lanes (e.g., the processing elementof the lane) is generally isolated from each of the other processinglanes. Embodiments of the vector coprocessor core 104 improve SIMDprocessing efficiency by providing communication between the processingelements 308 of the SIMD lanes.

Some embodiments of the vector coprocessor core 104 include logic thatcompares values stored in two registers of the vector register file 306associated with each SIMD processing lane. That is values of tworegisters associated with a first lane are compared, values of tworegisters associated with a second lane are compared, etc. The vectorcoprocessor core 104 packs the result of the comparison in each laneinto a data value, and broadcasts (i.e., writes) the data value to adestination register associated with each SIMD lane. Thus, theprocessing element 308 of each SIMD lane is provided access to theresults of the comparison for all SIMD lanes. The vector coprocessorcore 104 performs the comparison, packing, and broadcasting as executionof a vector bit packing instruction, which may be defined as:

-   VBITPK src1, src2, dst    where:    -   src1 and src2 specify the registers to be compared; and    -   dst specifies the register to which the packed comparison        results are to be written.

Some embodiments of the vector coprocessor core 104 include logic thatcopies a value of one register to another within each SIMD lane based ona packed array of flags, where each flag corresponds to an SIMD lane.Thus, given the packed flag value in a register, each SIMD laneidentifies the flag value corresponding to the lane (e.g., bit 0 of theregister for lane 0, bit 1 of the register for lane 1, etc.). If theflag value is “1” then a specified source register of the lane is copiedto a specified destination register of the lane. If the flag value is“0” then zero is written to the specified destination register of thelane. The vector coprocessor core 104 performs the unpacking of the flagvalue and the register copying as execution of a vector bit unpackinginstruction, which may be defined as:

-   VBITUNPK src1, src2, dst    where:    -   src1 specifies the register containing the packed per lane flag        values;    -   src2 specifies the register to be copied based on the flag value        for the lane; and    -   dst specifies the destination register to written.

Some embodiments of the vector coprocessor core 104 include logic thattransposes values of a given register across SIMD lanes. For example, asshown below, a given register in each of a 4-way vector coprocessor core104 contains the values 8, 4, 0×C, and 2. The vector coprocessor core104 transposes the bit values such that bit 0 values of each lane arewritten to the specified destination register of lane 0, bit 1 values ofeach lane are written to the specified destination register of lane 1,etc.

Source: bit position lane value 0 1 2 3 0 1 1 0 0 0 1 2 0 1 0 0 2 3 1 10 0 3 4 0 0 1 0

Destination: bit position lane value 0 1 2 3 0 5 1 0 1 0 1 6 0 1 1 0 2 80 0 0 1 3 0 0 0 0 0Thus, the vector coprocessor core 104 transposes the bits of the sourceregister across SIMD lanes. The vector coprocessor core 104 performs thetransposition as execution of a vector bit transpose instruction, whichmay be defined as:

-   VBITTR src1, dst    where:    -   src1 specifies the register containing the bits to be        transposed; and    -   dst specifies the register to which the transposed bits are        written.

Some embodiments of the processing element 308 include logic thatprovides bit level interleaving and deinterleaving of values stored inregisters of the vector register file 306 corresponding to theprocessing element 308. For example, the processing element 308 mayprovide bit interleaving as shown below. In bit interleaving the bitvalues of two specified source registers are interleaved in adestination register, such that successive bits of each source registerare written to alternate bit locations of the destination register.

src1=0×25 (0000_(—)0000_(—)0010_(—)0101),

src2=0×11 (0000_(—)0000_(—)0001_(—)0001),

dst=0×523 (0000_(—)0000_(—)0000_(—)0000_(—)0000_(—)1001_(—)0010_(—)0011)

The processing element 308 performs the interleaving as execution of avector bit interleave instruction, which may be defined as:

-   VBITI src1, src2, dst    where:    -   src1 and src2 specify the registers containing the bits to be        interleaved; and    -   dst specifies the register to which the interleaved bits are        written.

The processing element 308 executes deinterleaving to reverse theinterleaving operation described above. In deinterleaving, theprocessing element 308 writes even indexed bits of a specified sourceregister to a first destination register and writes odd indexed bits toa second destination register. For example:

src=0×523 (0000_(—)0000_(—)0000_(—)0000_(—)0000_(—)1001_(—)0010_(—)0011)

dst1=0×25 (0000_(—)0000_(—)0010_(—)0101),

dst2=0×11 (0000_(—)0000_(—)0001_(—)0001),

The processing element 308 performs the deinterleaving as execution of avector bit deinterleave instruction, which may be defined as:

-   VBITDI src, dst 1, dst 2,    where:    -   src specifies the register containing the bits to be        deinterleaved; and    -   dst1 and dst2 specify the registers to which the deinterleaved        bits are written.

Embodiments of the vector coprocessor core 104 may also interleaveregister values across SIMD lanes. For example, for 8-way SIMD, thevector coprocessor core 104 may provide single element interleaving oftwo specified source registers as:

dst1[0]=src1[0];

dst1[1]=src2[0];

dst1[2]=src1[1];

dst1[3]=src2[1];

dst1[4]=src1[2];

dst1[5]=src2[2];

dst1[6]=src1[3];

dst1[7]=src2[3];

dst2[0]=src1[4];

dst2[1]=src2[4];

dst2[2]=src1[5];

dst2[3]=src2[5];

dst2[4]=src1[6];

dst2[5]=src2[6];

dst2[6]=src1[7];

dst2[7]=src2[7];

where the bracketed index value refers the SIMD lane. The vectorcoprocessor core 104 performs the interleaving as execution of a vectorinterleave instruction, which may be defined as

-   VINTRLV src1/dst1, src2/dst2,    where src1/dst1 and src2/dst2 specify source registers to be    interleaved and the registers to be written.

The vector coprocessor core 104 may also interleave register valuesacross SIMD lanes with 2-element frequency. For example, for 8-way SIMD,the vector coprocessor core 104 may provide 2-element interleaving oftwo specified source registers as:

dst1[0]=src1[0];

dst1[1]=src1[1];

dst1[2]=src2[0];

dst1[3]=src2[1];

dst1[4]=src1[2];

dst1[5]=src1[3];

dst1[6]=src2[2];

dst1[7]=src2[3];

dst2[0]=src1[4];

dst2[1]=src1[5];

dst2[2]=src2[4];

dst2[3]=src2[5];

dst2[4]=src1[6];

dst2[5]=src1[7];

dst2[6]=src2[6];

dst2[7]=src2[7];

where the bracketed index value refers the SIMD lane. The vectorcoprocessor core 104 performs the 2-element interleaving as execution ofa vector interleave instruction, which may be defined as:

-   VINTRLV2 src1/dst1, src2/dst2,    where src1/dst1 and src2/dst2 specify source registers to be    interleaved and the registers to be written.

The vector coprocessor core 104 may also interleave register valuesacross SIMD lanes with 4-element frequency. For example, for 8-way SIMD,the vector coprocessor core 104 may provide 4-element interleaving oftwo specified source registers as:

dst1[0]=src1[0];

dst1[1]=src1[1];

dst1[2]=src1[2];

dst1[3]=src1[3];

dst1[4]=src2[0];

dst1[5]=src2[1];

dst1[6]=src2[2];

dst1[7]=src2[3];

dst2[0]=src1[4];

dst2[1]=src1[5];

dst2[2]=src1[6];

dst2[3]=src1[7];

dst2[4]=src2[4];

dst2[5]=src2[5];

dst2[6]=src2[6];

dst2[7]=src2[7];

where the bracketed index value refers the SIMD lane. The vectorcoprocessor core 104 performs the 4-element interleaving as execution ofa vector interleave instruction, which may be defined as:

-   VINTRLV4 src1/dst1, src2/dst2,    where src1/dst1 and src2/dst2 specify source registers to be    interleaved and the registers to be written.

Embodiments of the vector coprocessor core 104 provide deinterleaving ofregister values across SIMD lanes. Corresponding to the single elementinterleaving described above, the vector coprocessor core 104 providessingle element deinterleaving. For example, for 8-way SIMD, the vectorcoprocessor core 104 may provide single element deinterleaving of twospecified source registers as:

dst1[0]=src1[0];

dst2[0]=src1[1];

dst1[1]=src1[2];

dst2[1]=src1[3];

dst1[2]=src1[4];

dst2[2]=src1[5];

dst1[3]=src1[6];

dst2[3]=src1[7];

dst1[4]=src2[0];

dst2[4]=src2[1];

dst1[5]=src2[2];

dst2[5]=src2[3];

dst1[6]=src2[4];

dst2[6]=src2[5];

dst1[7]=src2[6];

dst2[7]=src2[7];

The vector coprocessor core 104 performs the deinterleaving as executionof a vector interleave instruction, which may be defined as:

-   VDINTRLV src1/dst1, src2/dst2,    where src1/dst1 and src2/dst2 specify source registers to be    deinterleaved and the registers to be written.

Corresponding to the 2-element interleaving described above, the vectorcoprocessor core 104 provides 2-element deinterleaving. For example, for8-way SIMD, the vector coprocessor core 104 may provide 2-elementdeinterleaving of two specified source registers as:

dst1[0]=src1[0];

dst1[1]=src1[1];

dst2[0]=src1[2];

dst2[1]=src1[3];

dst1[2]=src1[4];

dst1[3]=src1[5];

dst2[2]=src1[6];

dst2[3]=src1[7];

dst1[4]=src2[0];

dst1[5]=src2[1];

dst2[4]=src2[2];

dst2[5]=src2[3];

dst1[6]=src2[4];

dst1[7]=src2[5];

dst2[6]=src2[6];

dst2[7]=src2[7];

The vector coprocessor core 104 performs the 2-element deinterleaving asexecution of a vector interleave instruction, which may be defined as:

-   VDINTRLV2 src1/dst1, src2/dst2,    where src1/dst1 and src2/dst2 specify source registers to be    deinterleaved and the registers to be written.

The processing elements 308 are configured to conditionally move datafrom a first register to second register based on an iteration conditionof the nested loops being true. The conditional move is performed in asingle instruction cycle. The processing elements 308 perform theconditional move as execution of a conditional move instruction, whichmay defined as:

-   VCMOV cond, src, dst    where:    -   src and dst specify the register from which and to which data is        to be moved; and    -   cond specifies the iteration condition of the nested loops under        which the move is to be performed.

The loop iteration condition (cond) may specify performing the move:

-   -   on every iteration of the inner-most loop (loop M);    -   on the final iteration of the inner-most loop;    -   in loop M−1, prior to entering loop M;    -   in loop M−2, prior to entering loop M−1;    -   in loop M−3, prior to entering loop M−2;    -   on the final iteration of loops M and M−1; or    -   on the final iteration of loops M, M−1, and M−2.

The processing elements 308 are configured to conditionally swap datavalues between two registers in a single instruction cycle based on avalue contained in a specified condition register. Each processingelement 308 executes the swap based on the condition register associatedwith the SIMD lane corresponding to the processing element 308. Theprocessing elements 308 perform the value swap as execution of aconditional swap instruction, which may defined as:

-   VSWAP cond, src1/dst1, src2/dst2    where:    -   src1/dst1 and src2/dst2 specify the registers having values to        be swapped; and    -   cond specifies the condition register that controls whether the        swap is to be performed.        In some embodiments, the swap is performed if the least        significant bit of the condition register is set.

The processing elements 308 are configured to sort two values containedin specified registers in a single instruction cycle. The processingelement 308 compares the two values. The smaller of the values iswritten to a first register, and the larger of the two values is writtento a second register. The processing elements 308 perform the value sortas execution of a sort instruction, which may defined as:

-   VSORT2 src1/dst1, src2/dst2    where src1/dst1 and src2/dst2 specify the registers having values to    be sorted. The smaller of the two values is written to dst1, and the    larger of the two values is written to dst2.

The processing elements 308 include logic that generates a result valuefrom values contained in three specified registers. A processing element308 may, in a single instruction cycle, add three register values,logically “and” three register values, logically “or” three registervalues, or add two register values and subtract a third register value.The processing elements 308 perform these operations as execution ofinstructions, which may defined as:

-   VADD3 src1, src2, src3, dst    where:    -   src1, src2, and src3 specify the registers containing values to        be summed; and    -   dst specifies the register to which the summation result is to        be written.-   VAND3 src1, src2, src3, dst    where:    -   src1, src2, and src3 specify the registers containing values to        be logically “and'd”; and    -   dst specifies the register to which the “and” result is to be        written.-   VOR3 src1, src2, src3, dst    where:    -   src1, src2, and src3 specify the registers containing values to        be logically “or'd”; and    -   dst specifies the register to which the “or” result is to be        written.-   VADIF3 src1, src2, src3, dst    where:    -   src1 and src3 specify the registers containing values to be        summed;    -   src2 specifies the register containing a value to subtracted        from the sum of src1 and src3; and    -   dst specifies the register to which the final result is to be        written.

The table lookup unit 310 is a processing unit separate from theprocessing elements 308 and the histogram unit 312. The table lookupunit 310 accelerates lookup of data values stored in tables in thememories 110, 112, 114. The table lookup unit 310 can perform N lookups(where N is the number of SIMD lanes of the vector coprocessor core 104)per cycle. The table lookup unit 310 executes the table lookups in anested loop. The table lookup loop is defined by a VLOOP instructionthat specifies table lookup operation. The vector command specified byVLOOP and the associated vector instructions cause the table lookup unit310 to retrieve a specified set of values from one or more tables storedin the memories 110, 112, 114, and store the retrieved values in thememories 110, 112, 114 at a different specified location.

A table lookup vector command initializes address generators used toaccess information defining which values are to be retrieved from alookup table, used to lookup table location in memory 110, 112, 114, andused to define where the retrieved lookup table values are to be stored.In each iteration of the table lookup vector command, the table lookupunit 310 retrieves information identifying the data to be fetched fromthe lookup table, applies the information in conjunction with the lookuptable location to fetch the data, and stores the fetched data to memory110, 112, 114 for subsequent access by a compute loop executing on thevector coprocessor core 104. The table lookup unit 310 may fetch tabledata from memories 110, 112, 114 based on a vector load instruction asdisclosed herein, and store the fetched data to memories 110, 112, 114using a vector store instruction as disclosed herein. Embodiments of thetable lookup unit 310 may also fetch data from memories 110, 112, 114using a vector table load instruction, which may be defined as:

-   VTLD<type>_<m>TBL_<n>PT tbl_base[tbl_agen] [V2], V0, RND_SAT:    rnd_sat    where:    -   type specifies the data size (e.g., byte, half-word, word,        etc.);    -   _<m>TBL specifies the number of lookup tables to be accessed in        parallel;    -   _<n>PT specifies the number of data items per lookup table to be        loaded;    -   tbl_base specifies a lookup table base address;    -   tbl_agen specifies an address generator containing offset to a        given table;    -   V2 specifies a vector register containing a data item specific        offset into the given table;    -   V0 specifies a vector register to which the retrieved table data        is to be written; and    -   RND_SAT: rnd_sat specifies a rounding/saturation mode to be        applied to the table lookup indices.

As shown by the vector table lookup instruction, the table lookup unit310 may fetch one or more data values from one or more tablessimultaneously, where each of the multiple tables is located in adifferent bank of memories 110, 112, 114. Fetching multiple values froma table for a given index is advantageous when interpolation is to beapplied to the values (e.g., bilinear or bicubic interpolation). Someembodiments of the table lookup unit 310 constrain the number of tablesaccessed and/or data values accessed in parallel. For example, theproduct of the number of tables accessed and the number of data valuesretrieved per table may be restricted to be less than the number of SIMDlanes of the vector coprocessor core 104. In some embodiments, thenumber of data values retrieved per table access may be restricted to be1, 2, or 4. Table 1 below shows allowable table and value numbercombinations for some embodiments of an 8-way SIMD vector coprocessorcore 104.

TABLE 1 Table Lookup Constraints Number of parallel tables, Num itemsper lookup, num_par_tbl Table type num_data_per_lu 1 2 4 8 Byte 1 ✓ ✓ ✓✓ 2 ✓ ✓ ✓ 4 ✓ ✓ 8 ✓ Half word 1 ✓ ✓ ✓ ✓ 2 ✓ ✓ ✓ 4 ✓ ✓ 8 ✓ Word 1 ✓ ✓ ✓ ✓2 ✓ ✓ ✓ 4 ✓ ✓ 8 ✓

The histogram unit 312 is a processing unit separate from the processingelements 308 and the table lookup unit 310. The histogram unit 312accelerates construction of histograms in the memories 110, 112, 114.The histogram unit 312 provides construction of normal histograms, inwhich an addressed histogram bin entry is incremented by 1, and weightedhistograms, in which an addressed histogram bin entry is incremented bya value provided as an element in a weight array input. The histogramunit 312 can perform N histogram bin updates (where N is the number ofSIMD lanes of the vector coprocessor core 104) simultaneously. Thehistogram unit 312 executes the histogram bin updates in a nested loop.The histogram loop is defined by a VLOOP instruction that specifieshistogram operation. The vector command specified by VLOOP and theassociated vector instructions cause the histogram unit 312 to retrievehistogram bin values from one or more histograms stored in the memories110, 112, 114, increment the retrieved values in accordance with apredetermined weight, and store the updated values in the memories 110,112, 114 at the locations from which the values were retrieved.

A histogram vector command initializes the increment value by which theretrieved histogram bin values are to be increased, loads an index to ahistogram bin, fetches the value from the histogram bin from memory 110,112, 114, adds the increment value to the histogram bin, and stores theupdated histogram bin value to memory 110, 112, 114. Bin value andweights may be signed or unsigned. Saturation may be applied to theupdated histogram bin value in accordance with the type (e.g.,signed/unsigned, data size, etc.) in conjunction with the storeoperation. Vector load instructions, as disclosed herein, may be used toinitialize the increment value and load the bin index. Embodiments ofthe histogram unit 312 may fetch histogram bin values from memories 110,112, 114 in accordance with a histogram load instruction, which may bedefined as:

-   VHLD<type>_<m>HIST hist_base[hist_agen] [V2], V0, RND_SAT: rnd_sat    where:    -   type specifies the data size (e.g., byte, half-word, word,        etc.);    -   _<m> HIST specifies the number of histograms to be accessed in        parallel;    -   hist_base specifies a histogram base address;    -   hist_agen specifies an address generator containing offset to a        given histogram;    -   V2 specifies a vector register containing a histogram bin        specific offset into the given histogram;    -   V0 specifies a vector register to which the histogram bin value        is to be written; and    -   RND_SAT: rnd_sat specifies a rounding/saturation mode to be        applied to the histogram indices.

Embodiments of the histogram unit 312 may store updated histogram binvalues to memories 110, 112, 114 in accordance with a histogram storeinstruction, which may be defined as:

-   VHST<type>_<m>HIST V0, hist_base[hist_agen][V2]    where:    -   type specifies the data size (e.g., byte, half-word, word,        etc.);    -   _<m> HIST specifies the number of histograms to be accessed in        parallel;    -   V0 specifies a vector register containing the histogram bin        value to be written to memory;    -   hist_base specifies a histogram base address;    -   hist_agen specifies an address generator containing offset to a        given histogram; and    -   V2 specifies a vector register containing a histogram bin        specific offset into the given histogram.

Embodiments of the processor 100 may be applied to advantage in anynumber of devices and/or systems that employ real-time data processing.Embodiments may be particularly well suited for use in devices thatemploy image and/or vision processing, such as consumer devices thatthat include imaging systems. Such devices may include an image sensorfor acquiring image data and/or a display device for displaying acquiredand/or processed image data. For example, embodiments of the processor100 may be included in mobile telephones, tablet computers, and othermobile devices to provide image processing while reducing overall powerconsumption.

The above discussion is meant to be illustrative of the principles andvarious embodiments of the present invention. Numerous variations andmodifications will become apparent to those skilled in the art once theabove disclosure is fully appreciated. It is intended that the followingclaims be interpreted to embrace all such variations and modifications.

What is claimed is:
 1. A processor, comprising: a scalar processor core;and a vector coprocessor core coupled to the scalar processor core; thescalar processor core comprising: a program memory interface throughwhich the scalar processor retrieves instructions from a program memory,the instructions comprising scalar instructions executable by the scalarprocessor and vector instructions executable by the vector coprocessorcore; a coprocessor interface through which the scalar processor passesthe vector instructions to the vector coprocessor; the vectorcoprocessor core, comprising: a plurality of execution units; and avector command buffer configured to: decode the vector instructionspassed by the scalar processor core; determine whether vectorinstructions defining an instruction loop have been decoded; andinitiate execution of the instruction loop by one or more of theexecution units based on a determination that all of the vectorinstructions of the instruction loop have been decoded.
 2. The processorof claim 1, wherein the instruction loop comprises a plurality of nestedloops and the vector coprocessor core is configured to execute theplurality of nested loops without looping overhead.
 3. The processor ofclaim 1, wherein the vector coprocessor core is configured to executevector instructions only by execution of the vector instructions withinan instruction loop comprising a predetermined plurality of nestedloops.
 4. The processor of claim 1, wherein the scalar processor core isconfigured to execute the scalar instructions while the vectorcoprocessor core executes the vector instructions.
 5. The processor ofclaim 1, wherein the vector command buffer comprises storage for aplurality of vector commands, each of the vector commands comprisingnested loops of vector instructions; and the vector command buffer isconfigured to decode the vector instructions of a second vector commandpassed by the scalar processor core while the execution units execute afirst vector command.
 6. The processor of claim 1, wherein the scalarprocessor core is configured to service interrupts while stalledawaiting completion of execution of vector instructions by the vectorcoprocessor.
 7. The processor of claim 1, wherein the vector processorcore further comprises an operand memory interface configured tosimultaneously access a plurality of banks of memory, each of the banksorganized as a plurality of sub-banks of memory.
 8. The processor ofclaim 7, wherein the operand memory interface is configured tosimultaneously access the plurality of sub-banks of memory.
 9. Theprocessor of claim 7, wherein vector processor core further comprises aplurality of address generators, each of the address generatorsconfigured to provide an address for accessing one of the sub-banks ofmemory.
 10. The processor of claim 1, wherein the instruction loopcomprises an outermost loop about a plurality of nested loops, whereinthe vector coprocessor core is configured to change, with no overhead,at least one of a location in memory of data to processed by the nestedloops and a dimension of an array of data to be processed by the nestedloops.
 11. The processor of claim 1, wherein the vector coprocessor coreis configured to exit the instruction loop prior to execution of apredetermined number of iterations of the instruction loop; wherein thevector coprocessor core is configured to schedule the exit from apredetermined number of nested loops of the instruction loop to occur atcompletion of a current iteration of an innermost loop of the nestedloops based on a value stored in a register of the vector coprocessorcore.
 12. The processor of claim 1, wherein the vector coprocessor coreis configured to exit an outermost loop of the instruction loop prior toexecution of a predetermined number of iterations of the outermost loop;wherein the vector coprocessor core is configured to schedule the exitfrom the outermost loop to occur at completion of all iterations ofloops within the outermost loop based on a value stored in a register ofthe vector coprocessor core.
 13. A vector coprocessor, comprising: aplurality of execution units configured to simultaneously apply aninstruction specified operation to different data; and a vector commandbuffer configured to: decode instructions to be executed by theexecution units; identify an instruction loop in the instructions; andprovide the instructions to the execution units for execution based on adetermination that all of the instructions of an identified instructionloop have been decoded.
 14. The vector coprocessor of claim 13, furthercomprising loop control logic configured to control execution of aplurality of nested loop of the instruction loop without loopingoverhead.
 15. The vector coprocessor of claim 14, wherein the loopcontrol logic is configured to exit the instruction loop prior toexecution of a predetermined number of iterations of the instructionloop; wherein the loop control logic is configured to schedule the exitfrom the predetermined number of nested loops of the instruction loop tooccur at completion of a current iteration of an innermost loop of thenested loops based on a value read from a register of the vectorcoprocessor core during the current iteration of the innermost loop. 16.The vector coprocessor of claim 14, wherein the loop control logic isconfigured to exit an outermost loop of the instruction loop prior toexecution of a predetermined number of iterations of the outermost loop;wherein the loop control logic is configured to schedule the exit fromthe outermost loop to occur at completion of all iterations of nestedloops within the outermost loop based on a value read from a register ofthe vector coprocessor core during a current iteration of an innermostloop of the nested loops.
 17. The vector coprocessor of claim 14,wherein the instruction loop comprises an outermost loop about aplurality of nested loops, wherein the loop control logic is configuredto change, with no overhead, at least one of a distance to a next objectin memory to be processed by the nested loops and a dimension of thenext object to be processed by the nested loops.
 18. The vectorcoprocessor of claim 13, wherein the vector command buffer comprisesstorage for a plurality of vector commands, each of the vector commandscomprising nested loops of instructions; and the vector command bufferis configured to decode the instructions of a second vector commandwhile the execution units execute a first vector command.
 19. The vectorcoprocessor of claim 13, further comprising an operand memory interfaceconfigured to simultaneously access a plurality of banks of memory, eachof the banks organized as a plurality of sub-banks of memory.
 20. Thevector coprocessor of claim 16, wherein the operand memory interface isconfigured to simultaneously access the plurality of sub-banks ofmemory.
 21. The vector coprocessor of claim 16, further comprising aplurality of address generators, each of the address generatorsconfigured to provide an address for accessing one or more of thesub-banks of memory.
 22. The vector coprocessor of claim 13, vectorcommand buffer is configured to identify the instruction loop based ondetection of a looping instruction in the instructions, wherein thelooping instruction is indicative of a start of the instruction loop andspecifies a length of the instruction loop.
 23. The vector coprocessorof claim 13, further comprising: a processor interface through which thevector processor receives from a different processor: instructions to beexecuted by the vector processor; memory storage addresses of theinstructions to executed by the vector processor, wherein each addressis provided concurrently with one of the instructions; and data valuesto be written to a register of the vector processor, wherein each datavalue is provided concurrently with one of the instructions.
 24. Aprocessor, comprising: a control processor core; and asingle-instruction multiple data (SIMD) coprocessor core coupled to thecontrol processor core; the control processor core comprising: a programmemory interface through which the control processor retrievesinstructions from a program memory, the instructions comprisinginstructions executable by the scalar processor and SIMD instructionsexecutable by the SIMD coprocessor core; the SIMD coprocessor core,comprising: a plurality of execution units; and a vector command bufferconfigured to: group SIMD instructions received from the controlprocesser core into an instruction loop; and initiate execution of theinstruction loop based on a complete set of SIMD instructions of aninstruction loop being received from the control processor core; andloop control logic coupled to the vector command buffer, the loopcontrol logic configured to manage execution of the instruction loop asa plurality of nested loops without loop overhead.
 25. The processor ofclaim 24, wherein the control processor core is configured to: executeinstructions while the SIMD coprocessor core executes the instructionloop; and service interrupts while stalled awaiting completion ofexecution of the instruction loop.
 26. The processor of claim 24,wherein the vector command buffer comprises: an SIMD instructiondecoder; and storage for a plurality of vector commands, each vectorcommand comprising an instruction loop; wherein the SIMD instructiondecoder is configured to decode a vector command while a previouslydecoded vector command is being executed.
 27. The processor of claim 24further comprising: a plurality of banks of memory coupled to thecontrol processor core and to the SIMD coprocessor core, wherein eachbank of memory comprises a number of sub-banks equal to a number of SIMDprocessing lanes of the SIMD coprocessor core; wherein the SIMDcoprocessor core comprises a memory interface configured tosimultaneously access all the sub-banks of a given one of the banks ofmemory.
 28. The processor of claim 24, wherein the loop control logic isconfigured to: schedule exit from a predetermined number of nested loopsof the instruction loop to occur at completion of a current iteration ofan innermost loop of the nested loops based on a value read from aregister of the vector coprocessor core during the current iteration ofthe innermost loop; and schedule exit from an outermost loop of theinstruction loop to occur at completion of all iterations of the nestedloops within the outermost loop based on the value read from theregister of the vector coprocessor core during the current iteration ofthe innermost loop; wherein the current iteration is not the lastiteration of the instruction set at initiation of instruction loopexecution.
 29. The processor claim 24, wherein the loop control logic isconfigured to change, with no overhead, on execution of an outermostloop of the instruction loop, at least one of a distance to a nextobject in memory to be processed by the instruction loop and a dimensionof the next object to be processed by the instruction loop.